In recent years, progress has been made in improving integration density and performance of semiconductor devices, and fields of application thereof have been widely expanding. According to these situations, technical matters for reducing the power consumption of semiconductor devices or semiconductor chip bodies have been increasing in importance. More specifically, a data information device having a telephone, an electronic organizer, a small personal computer and/or the like in an integrated form is required to have an internal battery having a long duration. Further, a high-performance information processing device is required to have a cooling device and a power supply device of small sizes. In view of a social demand for protecting global environment by effectively using energy resources, the improvement of the performance as well as the reduction of the power consumption of the semiconductor device have been deemed as important elemental technologies for adding value to the semiconductor devices.
As an example of such technologies, there has been a semiconductor device which uses multiple kinds of thresholds, i.e., a so-called “Multi-Threshold CMOS (which may also be referred to as an “MTCMOS” hereinafter). An MTCMOS circuit is formed of a logic circuit group and transistors of high threshold voltages, and can prevent increase in power consumption in the logic circuit group when the logic circuit group formed of the CMOSs is on standby. In connection with this, Patent Documents 1-3 and Non-Patent Document 1 have disclosed various methods that reduce power consumption in a standby mode.
More specifically, the logic circuit group includes a logic circuit having a single or multiple logic gate(s) or the like. The logic gate is formed of a P-channel MOS transistor having a low threshold voltage and an N-channel MOS transistor having a low threshold voltage.
FIG. 46 illustrates a conventional MTCMOS circuit.
Referring to FIG. 46, logic circuit groups L1 and L2 are shown. For example, logic circuit group L1 has a structure in which P- and N-channel MOS transistors P2 and Q1 each having a low threshold voltage are connected between a pseudo-power supply line VA1 on a high potential side and a pseudo-ground line VB1 on a low potential side.
Pseudo-power supply line VA1 is connected to a true power supply Vcc via a P-channel MOS transistor P1 having a high threshold. Pseudo-ground line VB1 is connected to a true ground voltage GND via an N-channel MOS transistor Q2 having a high threshold. Transistor P1 receives on its gate a control signal /Sleep3, and transistor Q2 receives on its gate a control signal Sleep3 that is an inverted signal of control signal /Sleep3.
Logic circuit group L2 has substantially the same structure. Although not shown, it is formed of transistors of a low threshold. Logic circuit group L2 is connected between a pseudo-power supply line Va2 on a high potential side and a pseudo-ground line VB2 on a low potential side. Pseudo-power supply line VA2 is connected to true power supply Vcc via a P-channel MOS transistor P3 having a high threshold. Also, pseudo-ground line VB2 is connected to true ground voltage GND via an N-channel MOS transistor Q3 having a high threshold. Transistor P3 receives on its gate a control signal /Sleep1, and transistor Q3 receives a control signal Sleep1 that is an inverted signal of control signal /Sleep1.
FIG. 47 is a timing chart of control signals Sleep1 and Sleep3 that operate the MTCMOS circuit.
As shown in FIG. 47, control signals Sleep1 and Sleep3 attain “H” and “L” levels at a time ta, respectively. Thereby, logic circuit group L1 attains a standby mode. Logic circuit group L2 is in an active mode.
More specifically, control signals Sleep3 and /Sleep3 to logic circuit group L1 attain the “L” and “H” levels, respectively. Thereby, pseudo-power supply line VA1 is electrically decoupled from power supply voltage Vcc. Also, pseudo-ground line VB1 is electrically decoupled from ground voltage GND. Control signals Sleep1 and /Sleep1 to logic circuit group L2 attain the “H” and “L” levels, respectively, so that transistors P3 and Q3 are turned on to couple electrically pseudo-power supply line VA2 and pseudo-ground line VB2 to power supply voltage Vcc and ground voltage GND, respectively.
Thereby, a current is supplied to pseudo-power supply line VA2 and pseudo-ground line VB2 via a current path of a low resistance, and logic circuit group L2 can operate.
At a subsequent time tb, control signal Sleep3 attains the “H” level so that logic circuit group L1 attains the active mode. More specifically, control signals Sleep3 and /Sleep3 to logic circuit group L1 attain the “H” and “L” levels, and thereby turn on transistors P1 and Q2, respectively. Since transistors P1 and Q2 are turned on, pseudo-power supply line VA1 and pseudo-ground line VB1 are electrically coupled to power supply voltage Vcc and ground voltage GND, respectively.
At a subsequent time tc, control signal Sleep1 attains the “L” level so that logic circuit group L2 attains the standby mode. More specifically, control signals Sleep1 and /Sleep1 to logic circuit group L2 attain the “L” and “H” levels, and thereby turn off transistors P3 and Q3, respectively.
This results in a state in which power supply voltage Vcc and ground voltage GND are electrically decoupled from pseudo-power supply line VA2 and pseudo-ground line VB2, respectively.
In general, a leak current preventing capability lowers with lowering of a threshold voltage of a transistor. Thus, power consumption of transistors P2, Q1 and the like increases. Therefore, the above circuit structure that generates leak currents in transistors P1, P3, Q2 and Q3 can reduce the power consumption in the standby mode. More specifically, in logic circuit groups L1 and L2, even when the structure uses transistors having low threshold voltages, this structure can suppress leak currents in transistors of a logic circuit group, and therefore can reduce the power consumption of the whole circuit.    Patent Document 1: Japanese Patent Laying-Open No. 09-064715    Patent Document 2: Japanese Patent Laying-Open No. 09-321600    Patent Document 3: Japanese Patent Laying-Open No. 2000-059200    Non-Patent Document 1: Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel and Kevin Stawiasz, “Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode”, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 20-25, 2004.